In the design of modern motor vehicles and also in mechanical engineering, e.g., in the machine-tool sector, and therefore also in automation, the networking of control devices, sensor apparatus, and actuator apparatus with the aid of a communication system and a bus system, i.e., a communication connection, has drastically increased in recent years. Synergistic effects can be achieved by distributing functions among multiple control devices, the term “distributed systems” being used. Communication among different stations takes place more and more via a bus system, i.e. a communication system. Communication traffic on the bus system, access and reception mechanisms, and error handling are regulated by way of a protocol. A known protocol for this purpose is the CAN protocol or the TTCAN protocol, as well as the FlexRay protocol, e.g., the FlexRay protocol specification v. 2.0. FlexRay is a fast, deterministic, and error-tolerant bus system for use in particular in a motor vehicle. The FlexRay protocol operates with the time division multiple access (TDMA) method; the components, i.e., subscribers and messages to be transferred, are assigned fixed time slots in which they have exclusive access to the communication connection. This is also implemented in comparable fashion in TTCAN. The time slots repeat in a defined cycle, so that the point in time at which a message is transferred via the bus can be exactly predicted, and bus access occurs deterministically. To optimize the utilization of bandwidth for message transfer on the bus system, FlexRay divides the cycle into a static and a dynamic part. The fixed time slots are located in the static part at the beginning of a bus cycle. The time slots are allocated dynamically in the dynamic part, and exclusive bus access is enabled in them only for a short period in each case (“mini-slots”). Only when a bus access occurs within a mini-slot is the time slot lengthened by the requisite amount. The result is that bandwidth is consumed only when it is actually needed. FlexRay communicates via two physically separate lines, each having a maximum data rate of 10 MB per second. The two channels correspond to the physical layer of, in particular, the Open System Architecture (OSI) layer model. These channels serve principally for redundant (and therefore error-tolerant) transfer of messages, although different messages can also be transferred, which would then result in a doubling of the data rate. FlexRay can also, however, be operated at lower data rates.
In order to implement synchronous functions and to optimize bandwidth by way of small spacings between two messages, the distributed components in the communication network, i.e., the subscribers, require a shared time base (called “global time”). For clock synchronization purposes, synchronization bulletins are transferred in the static part of the cycle; using a special algorithm meeting the FlexRay specification, the local clock time of a component is corrected in such a way that all the local clocks run synchronously with a global clock. This synchronization is also accomplished in comparable fashion in a TTCAN network.
A FlexRay network node or FlexRay subscriber or host contains a subscriber processor, i.e., the host processor, a FlexRay controller or communication controller, and (in the context of bus monitoring) a bus guardian. The host processor, i.e., the subscriber processor, furnishes and processes the data that are transferred via the FlexRay communication controller. For communication in a FlexRay network, messages or message objects can be configured with, for example, up to 254 data bytes. A communication module, in particular a communication controller, is then used to transfer these messages or message objects between the physical layer (i.e. the communication connection) and the host processor.
Accesses to the message memory of a communication module of, in particular, a FlexRay communication controller occur both by way of the host processor unit, i.e. the host CPU, and via interface modules to the physical layer. Access to the host CPU encompasses the writing and reading of configuration data, status data, and the actual data to be sent. Access to the interface modules to the physical layer encompasses the reading of transmission messages and the storage of received messages; in both cases, the integrity of the messages must be ensured by way of suitable actions.
It is therefore an object of the invention to optimize data transfer between the host CPU, i.e., the subscriber processor, and the message memory in terms of transfer speed and data integrity.